2025 3D-PEIM Plenary Speakers

Plenary P1:
Title: “Beyond 2030, Powering the E-Powertrain with a High Value and High Efficiency Power Conversion Systems, A Borgwarner Perspective”
Presenter: Harsha Nanjundaswamy, BorgWarner

Abstract: Adaptation of electric propulsion across all vehicle classes is moving at a rapid pace, although the penetration rates appear slower than expected, beyond 2030, and towards 2040 the adoption becomes a necessity to keep the commitments to CAFE and GHG compliance. As we move towards 2035, a greater emphasis on efficiency and cost is becoming even more important, in power conversion systems finding design synergies between efficiency and cost is the winning strategy. Besides battery, Electric Drive Unit (EDU), Chargers and Converters play a crucial role in EV energy ecosystem. BorgWarner is at the center of it all, while we provide compelling e-product solutions to OEMs across the globe to help meet their commitments in a profitable manner. Synergy is key, e-Products are designed with system level synergy around Value, Efficiency, Compactness and Versatility. Engineering for manufacturing and supply chain resilience while achieving excellent product value in today’s demand for localization within the global economy is becoming a crucial element to consider.

Biography:

Harsha NanjundaswamyHarsha Nanjundaswamy is a Global Chief Engineer of Advanced E-Drive and Power Electronics at BorgWarner. He oversees the development of next generation electric drive solutions and power conversion devices which complement BorgWarner’s electrification product portfolio. Prior to joining BorgWarner Mr. Nanjundaswamy was the Director of E-Mobility division at FEV North America Inc. He has over 20+ years of automotive experience, he started his career at Bosch in 1999. He received his MS from the University of Michigan Ann Arbor.


Plenary P2:
Title: “Advanced Packaging to System Integration – Trends and Challenges”
Presenter: Devan Iyer, IPC

Abstract: Advanced packaging is a critical part of the design and manufacture of chips, not only to manage the heat generated and deliver power effectively but also as a way to enhance system miniaturization and performance. Advanced packaging solutions are becoming even more critical now as the strategy of adding more transistors on ever smaller chips, the practice that has driven the industry since the 1960s, reaches both its financial and physical limits. Several advanced packaging technologies that have arisen over the past two decades—including 2.5-D, 3-D, fan-out, medium and high-power packaging and heterogeneously integrated multi-chip packaging are helping to meet the demand for semiconductors that run emerging applications like data centers, 5G/6G wireless communications, autonomous vehicles, IoT technologies , and virtual / augmented reality applications. Salient aspects of these technologies will be outlined during the talk.

In addition, the assembly of these advanced packages to PCBs creates additional challenges from the system integration perspective. The chip- package-PCB co- design, from electrical, thermal, mechanical design perspective, needs for innovative materials and assembly processes will be explored during this talk. Some of the challenges and possible risk mitigation paths will also be discussed.

Biography:

Devan IyerDevan Iyer is a Chief Strategist – Advanced Packaging at IPC International Inc. since March 2024. He has more than 38 years of experience in semiconductor packaging, assembly engineering and test. More recently, he has held Senior vice president and Vice president positions at Amkor Technologies and Texas Instruments Inc respectively leading businesses, advanced packaging, assembly and test organizations. He has worked at Infineon Technologies and General Electric prior to joining Texas Instruments. Devan has also spent few years at Institute of Microelectronics, Singapore and Georgia Tech packaging research center, Atlanta running industry consortia activities.


Plenary P3:
Title: “The Power Delivery and Energy Storage Challenge in Advanced Packaging”
Presenter: Subramanian S. Iyer, University of California, Los Angeles

Abstract: The power requirements of modern computing systems are indeed colossal with gigawatt Data Centers not too far away. While generating that power itself is a monumental challenge, the challenge of delivering that power to the circuits that do the work, is just as formidable, as it must be delivered at extremely low operating voltages with utmost efficiency. This and the converse problem of heat dissipation have been referred to as the “Achilles Heel” of advanced packaging in the NAPMP vision paper. This is exacerbated by the challenge of “scale-down and scale-out” outlined in the NAPMP vision paper. The requirements of the power delivery network include low impedance from DC to GHz frequencies, a stiff power grid in three dimensions, the ability to switch from standby to over voltage in a fraction of clock cycle, extreme fault tolerance for large systems and the ability to anticipate and react to rapidly shifting workloads. Thus, the power delivery subsystem is perhaps even more complex and heterogeneous than the complex system it services! Fortunately, advanced packaging can come to the rescue and offer innovative solutions at a highly granular level. The ability to integrate diverse semiconductor material systems and devices that operate over a large range of voltages and frequencies, embedded high density passive elements such as capacitors and inductors and extremely short distances made possible by 3D vertical integration as well as smart substrates make for some very innovative solutions. Another equally important problem is energy generation and storage in low power edge systems, such as wearable electronics, where again advanced packaging can provide innovative solutions. In this talk we will explore these spaces and outline current thinking on addressing these issues.

Biography:

Subramanian IyerSubramanian “Subu” Iyer is a distinguished professor at the University of California at Los Angeles (UCLA) and founded UCLA CHIPS. He was responsible for driving the technical strategy behind the National Advanced Packaging Manufacturing Program as Director while on assignment from UCLA. Prior to joining UCLA, he was a Fellow at IBM and drove key innovations in semiconductor and packaging technology from concept to product delivery. He is Fellow of IEEE, APS, iMAPs and NAI.

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